1. Field of the Invention
The present invention relates to a light-emitting display device provided with a display panel on which active driving of light-emitting elements forming pixels are performed by, for example, thin film transistors (TFTs), and, especially, to a light-emitting display device, and a driving control method therefor, by which deterioration in image quality displayed can be effectively prevented by a ripple component which is superimposed on a driving power of the display panel.
2. Description of the Related Art
Development of a light-emitting display device using a display panel with a configuration in which light-emitting elements are arranged like a matrix has been widely promoted, and, for example, an organic electroluminescence (EL) element which uses an organic material for a light-emitting layer has received widespread attention as a light-emitting element used for such a display panel. The background for such attention is that the organic EL element has higher efficiency and longer life by using an organic compound, which is expected to have preferable characteristics fit for practical use, for a light-emitting layer of the EL element.
A direct matrix type display panel on which the EL elements are simply arranged like a matrix, and an active element comprising the TFT are added to each of the EL elements arranged like a matrix an active matrix type display panel have been proposed as a display panel using such an organic EL element. The power consumption of the latter active matrix type display panel can be lower than that of the former direct matrix type display panel. Moreover, the latter panel has characteristics such as less crosstalk between pixels, and is suitable, especially, for a high resolution display forming a large screen.
FIG. 1 shows one example of a light-emitting display device provided with a basic circuit structure corresponding to one pixel on a conventional active matrix type display panel, and a driving circuit for the circuit structure, and a power supply circuit which supplies driving power to the display panel provided with many pixels which have been described above. Here, a display panel 1 shown in the drawing has a circuit structure including one pixel 2 on account of limited space. The circuit structure including one pixel 2 is the most basic pixel configuration called a conductance controlled method, and the configuration uses an organic EL element as a light-emitting element.
That is, a gate electrode (Hereinafter, simply called a gate) of an N channel type selection scanning transistor Tr1 comprising TFT is connected to a scanning line (scanning line A1), and, a source electrode (Hereinafter, simply called a source) is connected to a data line (data line B1).
Moreover, the drain electrode (hereinafter, simply called drain) of the above selection scanning transistor Tr1 is connected to the gate of a P channel type light-emitting driving transistor Tr2, and, at the same time, to one terminal of a capacitor Cs for charge conservation.
The light-emitting driving transistor Tr2 has a configuration in which the source is connected to the other terminal of the capacitor Cs, and, at the same time, driving power Va (hereinafter, also called a driving voltage Va) from a DC-DC converter described below is supplied to the source through a power supply line P1 arranged on the display panel 1. Moreover, the drain of the light-emitting driving transistor Tr2 is connected to the anode terminal of an organic E1 element E1, and the cathode terminal of the organic EL element E1 is connected to a reference potential point (ground) in the example shown in FIG. 1.
According to the circuit structure of the pixel 2, the selection scanning transistor Tr1 is put into an ON-state when a selection voltage Select is supplied to the gate of the selection scanning transistor Tr1 through the scanning line A1 in an address period (data writing period). Then, a current corresponding to a data voltage Vdata flows from the source to the drain in the selection scanning transistor Tr1 when the data voltage Vdata corresponding to writing data from the data line B1 is supplied to the source of the selection scanning transistor Tr1. Accordingly, the above-described capacitor Cs is charged in a period in which the selection voltage Select is applied to the gate of the transistor Tr1, and the charging voltage is corresponding to the data voltage Vdata.
On the other hand, the charging voltage at which the above-described capacitor Cs is charged is supplied to the above-described light-emitting driving transistor Tr2 as a gate voltage, and a current based on the gate voltage and the driving voltage Va supplied through the power supply line P1 which is the source voltage flows from the drain to the EL element E1 in the light-emitting driving transistor Tr2 to drive the EL element E1 for light-emitting by the drain current.
Here, when the addressing operation corresponding to one scanning line is completed, and the gate potential of the selection scanning transistor Tr1 reaches an OFF voltage, the transistor Tr1 concerned is put into a so-called cut-off state, and the drain side of the transistor Tr1 is put into an open state. However, the voltage of the light-emitting driving transistor Tr2 is kept at the gate voltage by charges accumulated in the capacitor Cs, the same driving current is maintained before the data voltage Vdata is rewritten in the subsequent address period, and the light-emitting state, which is based on this driving current, of the EL element E1 is continued.
The configuration of the pixel 2 forms a dot matrix type display panel on which multiple pixels are arranged on the display panel 1 shown in FIG. 1 like a matrix, and each pixel 2 is formed at intersecting positions of scanning lines A1, - - - , and data lines B1, - - - .
Image signals displayed in the light-emitting display panel 1 is supplied to a light-emitting control circuit 4 shown in FIG. 1. In this light-emitting control circuit 4, based on horizontal, and vertical synchronizing signals in the image signals, input image signals are converted into corresponding pixel data every one pixel through sampling processing for sequential writing operation into a not-shown frame memory. Then, in an address period after the writing processing of pixel data for one frame into a frame memory is completed, serial pixel data, which has been read out from the frame memory every one scanning line described above, and shift clock signals are supplied to a shift register and data latch circuit 5a in a data driver 5 one by one.
This shift register and data latch circuit 5a has a configuration in which pixel data corresponding to one horizontal scanning is taken for latching, using the shift clock signals, and a latch output corresponding to one horizontal scanning is supplied to a level shifter 5b as parallel data. By the above configuration, data voltage Vdata corresponding to the pixel data is configured to individually be supplied to the source of the selection scanning transistor Tr1 forming each pixel 2. And, the operations are repeated everyone scanning in the address period.
Moreover, a scanning shift clock signal corresponding to the horizontal synchronizing signal is supplied from the light-emitting control circuit 4 to the scanning driver 6 in the address period. This scanning shift clock signal is supplied to a shift register 6a and to generate a register output one by one. Then, the register output is converted with a level shifter 6b to a predetermined operation level, and is output to the scanning lines A1 - - - . By this operation, the selection voltage Select is configured to be supplied to the gate of the selection scanning transistor Tr1 forming each pixel 2 every scanning line one by one.
Accordingly, every one scanning in the address period, the selection voltage Select is supplied from the scanning driver 6 to each pixel 2 arranged on the scanning line in the display panel 1 is supplied. The data voltage Vdata is supplied to pixels 2 arranged every scanning line from the level shifter 5b in the data driver 5 in synchronization with the above supplying, and the gate voltage corresponding to the data voltage Vdata is written into each pixel corresponding to the scanning lines concerned (that is, the capacitors Cs). Then, an image corresponding to one frame is reproduced on the display panel 1 by execution of the above operations for all the scanning line.
On the other hand, the driving voltage Va is configured to be supplied from a DC-DC converter (DC: direct current) represent by a reference numeral 8 to each pixel 2 arranged on the display panel 1 through the power supply line P1, - - - . Moreover, according to the configuration shown in FIG. 1, the DC-DC converter 8 is configured to boost the output of a DC voltage source Ba on the primary side, using a pulse width modulation (PWM) control method.
This DC-DC converter 8 has a configuration in which PWM waves output from a switching regulator circuit 9 performs ON control of a MOS type power field effect transistor (FET) Q1 as a switching element at a predetermined duty cycle. That is, electric power energy from the DC voltage source Ba on the primary side is accumulated in an inductor L1 by ON operation of the power FET Q1. By OFF operation of the power FET Q1, the electric power energy accumulated in the inductor L1 is accumulated in a smoothing capacitor C1 through a diode D1. Then, the boosted DC output can be obtained as a terminal voltage of the capacitor C1 by repeating the ON and OFF operations of the power FET Q1.
The DC output voltage is divided by a thermistor TH1 for temperature compensation, and resistances R11 and R12, and is supplied to an error amplifier 10 in the switching regulator circuit 9. In this error amplifier 10, the divided output is compared with a standard voltage Vref, and an compared output (error output) is supplied to a PWM circuit 11. A triangular wave for PWM is generated, based in an oscillation signal from an oscillator 12, in this PWM circuit 11. This PWM wave performs a switching operation of the power FET Q1 for feedback control in such a way that the output voltage is kept at a predetermined driving voltage Va. Accordingly, the output voltage of the DC-DC converter, that is, the driving voltage Va can be represented by the following Formula 1:Va=Vref×[(TH1+R11+R12)/R12]  (Formula 1)
Here, the pixel configuration shown in FIG. 1 and the configuration of the driving circuit in the pixel configuration have been disclosed in Japanese Patent Publication No. 2003-316315 which was filed by the present inventor, and the DC-DC converter shown in FIG. 1 has also been disclosed in Japanese Patent Publication No. 2002-366101 which was filed by the present inventor.
Incidentally, a drain current Id by which the organic EL element E1 is driven for light-emitting is decided by a difference voltage (voltage between the gate and the source of the transistor Tr2=Vgs) between the driving voltage Va supplied through the power supply line P1 and the gate voltage of the driving transistor Tr2 decided by charges accumulated in the capacitor Cs in the configuration of the pixel 2 shown in FIG. 1. FIG. 2 shows an equivalent circuit for the pixel configuration. In FIG. 2, a switch SW1 is substituted for the selection scanning transistor Tr1 which has already been explained. Moreover, in FIG. 2 the data voltage Vdata transmitted through the data line B1 is equivalently represented by the gate voltage Vgate of a changeable voltage source.
Here, the boosting voltage of the DC-DC converter is used as the driving voltage Va supplied to the source of the transistor Tr2 as already explained, and it is unavoidable to some extent that ripple noise (ripple component) is superimposed on the voltage Va, because switching operations are required as an operating principle in this kind of DC-DC converters. Here, when a smoothing capacitor C1 with large capacitance is used, the level of the ripple component can be more reduced in the DC-DC converter, but the reducing effect of the ripple component cannot be expected too much in comparison with the increasing rate of the capacitance.
Especially, not only the increased cost, but also the larger volume for a capacitor is required in order to use the capacitor for a cellular telephone and a personal digital assistance (PDA), though the demand for the display panel shown in FIG. 1 and the DC-DC converter which drives the panel has been grown as a cellular telephone and PDA have been widely used. Accordingly, there is a practical limitation in designing the smoothing capacitor with controlled capacitance to some extent.
Therefore, a driving voltage, which is represent by Va as shown in FIG. 3, on which the ripple component corresponding to the switching period (boosting period Si) of the DC-DC converter is superimposed is supplied to the source of the light-emitting driving transistor Tr2 in the equivalent circuit shown in FIG. 2. On the other hand, the switch SW1 is turned on at addressing (at data writing), and a gate voltage Vgate according to an image signal is supplied to the gate of the driving transistor Tr2.
Here, Ls in FIG. 3 represents one scanning (line) period in the display panel and Fs indicates . . . frame period. As switching is independently operated in the DC-DC converter regardless of one scanning period in the display panel, a writing voltage, which is different among scanning lines in the voltage Vgs between the gate and the source under influence of the ripple component, is written into the capacitor Cs of each pixel.
That is, as shown in FIG. 3, data according to the voltage, which is represented as Vgs1, between the gate and the source is written into the capacitor Cs of each pixel corresponding to, for example, a first scanning line, data according to the voltage, which is represented as Vgs2, between the gate and the source is written to the capacitor Cs of each pixel corresponding to, for example, a second scanning line, and data according to the voltage, which is represented as Vgs3, between the gate and the source is written to the capacitor Cs of each pixel corresponding to, for example, a third scanning line.
FIG. 4 shows a Vgs-Id characteristic (characteristic concerning relation between voltages between the gate and the source, and drain currents) of TFT represented by the transistor Tr2. When the voltage between the gate and the source is changed within a range of delta-Vgs, the drain current is also changed within a range of delta-Id. Here, it has been known that the organic EL element has a characteristic by which the light-emitting intensity is approximately proportional to the current value flowing in the element concerned.
Accordingly, there occurs a state that the values Vgs are different from one another under influence of the ripple component corresponding to the timing of addressing as described above. As a result, each EL element on the light-emitting display panel 1 has different light-emitting intensity for each scanning line. Thereby, there can be presented a problem that the display quality of images is remarkably reduced, for example, a fine striped pattern, or flickering phenomenon is generated on the display panel.
In order to avoid such a problem, there can be an idea that, for example, a regulator circuit shown in FIG. 5 is adopted. That is, the regulator circuit shown in FIG. 5 is inserted between the output terminal of the DC-DC converter and the power supply lines P1, - - - , on the display panel 1. The regulator circuit shown in FIG. 5 comprises: a NPN transistor Q2; an error amplifier including an operational amplifier OP1; and a reference voltage source Vref1. Based on the above configuration, the emitter potential of the NPN transistor Q2 is supplied to a noninverting input terminal of the operation amplifier OP1, and the potential of the reference voltage source Vref1 is supplied to an inverting terminal of the operation amplifier OPI.
According to the configuration, a ripple component generated on the emitter side of the transistor Q2 is output to the error amplifier with the operation amplifier OPI. The base potential of the transistor Q2 is configured to be changed according to the output of the error amplifier. As a result, the emitter side, that is, the Vout side of the transistor Q2 can obtain an output voltage in which the ripple component is almost removed. However, the regulator circuit always causes power loss of (Vin−Vout)×Iout=P[w]. Accordingly, the duration time of a battery is remarkably reduced to cause a state in which it is difficult to adopt the above-described portable equipment.